EEPW论坛

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity color is port( clk : in std_logic; md : in std_logic;--模式选择 hs,vs,r,g,b : out std_logic); end color; architecture behav of color is signal hs1,vs1,fclk,cclk : std_logic; signal mmd : std_logic_vector(1 downto 0); signal fs : std_logic_vector(3 downto 0); signal cc : std_logic_vector(4 downto 0); --行同步/横彩条生成 signal ll : std_logic_vector(8 downto 0); --场同步/竖彩条生成 signal grbx : std_logic_vector(3 downto 1); --X横彩条 signal grby : std_logic_vector(3 downto 1); --Y竖彩条 signal grbp : std_logic_vector(3 downto 1); --输出彩条 signal grb : std_logic_vector(3 downto 1); begin grb(1)23) then --62.5K hs1479) then --97.65625HZ vs1