顶层文件是什么？一下模块对不对
控制模块
library ieee;
use ieee. std_ logic_1164. all;
entity sxzl0 is
port( a,clr, clk:in std_logic;
q:out std_logic);
end sxzl0;
architecture sxzl0 arc of sxzl0 is
begin
process(clk)
variable tmp:std_logic;
begin
if(clr='0')then
tmp:=0;
elsif(clk' event and clk='1')then
if(a='l')then
tmp:=not tmp;
end if;
end if;
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