我用MODELSIM XE6.0仿真18位定点转浮点运算，编译环境为ISE8.1 结果错误为：
# ** Error: fit_tbw.vhw(83): Subprogram '/=' is ambiguous. Suitable definitions exist in packages 'std_logic_signed' and 'std_logic_unsigned'.
# ** Error: fit_tbw.vhw(129): VHDL Compiler exiting
# ** Error: d:/Modeltech_xe_starter/win32xoem/vcom failed.
但是同样的程序在编译环境ISE6.3中用MODELSIM XE6.0 仿真不出错。
想请教高手这是为什么？ 谢谢！！！！！！
最佳回复
1楼
This occurs because the function is being defined in two libraries. Use the "-explicit" option to resolve the function. The "-explicit" option specifies to ignore an error in packages supplied by other EDA vendors; it directs the compiler to resolve ambiguous function overloading in favor of the explicit function definition. Command Line Example vcom -explicit .vhd Setting this Option in the ModelSim GUI 1. Open the compilation window by clicking "Compile". 2. Click Default Options. 3. Select the VHDL tabulation. 4. Check the box to "Use explicit declaration only". 5. Click Apply.
最新人才
广东 深圳
