ERROR:Route:472 -
This design is unrouteable.
To evaluate the problem please use fpga_editor.
WARNING:Par:100 - Design is not completely routed. There are 27 signals that are not
completely routed in this design. See the "serdes_top.unroutes" file for a list of
all unrouted signals. Check for other warnings in your PAR report that might
indicate why these nets are unroutable. These nets can also be evaluated
in FPGA Editor by selecting "Unrouted Nets" in the List Window.
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module serdes_top( input CE,CLK,CLKDIV,D1,D2,D3,D4,D5,D6,D7,D8,OCLK,SR, output Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8 ); wire OQ; oserdes_top U1 ( .OCE1(CE), .CLK(CLK), .CLKDIV(CLKDIV), .OQ1(OQ), .SR1(SR), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .D8(D8) ); iserdes_top U2 ( .CE(CE), .CLK(CLK), .CLKDIV(CLKDIV), .D(OQ), .OCLK(OCLK), .SR(SR), .Q1(Q8), .Q2(Q7), .Q3(Q6), .Q4(Q5), .Q5(Q4), .Q6(Q3), .Q7(Q2), .Q8(Q1) ); endmodule 该怎么改呢
2楼
现在解决了么？我也遇到了问题，加个好友给指导下吧qq524328403
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