EEPW论坛

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_arith.all; ENTITY CHUFA IS GENERIC(bit_b:integer:=21;bit:integer:=21); PORT(CLK:IN STD_LOGIC; BEICHUSHU_bcd:IN integer range 2097150 downto 0;--BIT_B-1 CHUSHU_bcd:IN integer range 2097150 downto 0;--BIT-1 SHANG_bcd:OUT integer range 2097150 downto 0);--BIT_B-1 END CHUFA; ARCHITECTURE chufa OF CHUFA IS SIGNAL DIV:STD_LOGIC_VECTOR(BIT DOWNTO 0);--CHUSHU'LENGTH+1==BIT SIGNAL BEICHUSHU: STD_LOGIC_VECTOR(BIT_B-1 DOWNTO 0);--BIT_B-1 SIGNAL CHUSHU: STD_LOGIC_VECTOR(BIT-1 DOWNTO 0);--BIT-1 SIGNAL SHANG: STD_LOGIC_VECTOR(BIT_B-1 DOWNTO 0); BEGIN BEICHUSHU=DIV THEN SHANG(I)'0'); END PROCESS; END chufa;

bullshit！

http://www.ece.uvic.ca/~ceng450l/vdiv.html http://www.vlsibank.com/sessionspage.asp?titl_id=3716

http://www.cs.umbc.edu/portal/help/VHDL/samples/samples.html

百度一下

学习

学习一下

看起不出来是啥