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http://www.pudn.com/downloads166/sourcecode/embed/detail758604.html

LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY PULSEf IS --脉冲形成器 port(clk4,bj: in std_logic; out4: out std_logic); end PULSEf; ARCHITECTURE MM OF PULSEf IS COMPONENT and PORT(a,b:IN STD_LOGIC; O: OUT STD_LOGIC); END COMPONENT and; COMPONENT nand PORT(a: IN STD_LOGIC; o: OUT STD_LOGIC); END COMPONENT nand; COMPONENT latch PORT( d,ena: IN STD_LOGIC; q1: OUT STD_LOGIC); END COMPONENT latch; SIGNAL g, e: std_logic; begin m1: and port map(a=bj,b=e,o=out4); m2: nand port map(a=g,o=e); m3: latch port map(d=bj,q1=g,ena=clk4); END MM; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand IS --非门 PORT (a: IN std_logic; o: OUT std_logic); END entity nand; ARCHITECTURE one OF nand IS Begin o

这貌似是基础的知识

应该能找到很多例子

应该比较基础了

是基础的知识

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